Texas Instruments LMK04368-EP Ultra-Low-Noise Jitter Cleaner
Texas Instruments LMK04368-EP Ultra-Low-Noise Jitter Cleaner is a high-performance clock conditioner with JEDEC JESD204B/C support for space applications. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using SYSREF or device clocks. SYSREF can be provided using both AC and DC coupling. These devices are not limited to JESD204B/C applications. Each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The Texas Instruments LMK04368-EP can be configured for operation in single PLL, dual PLL, or clock distribution modes with or without reclocking or SYSREF generation. PLL2 may operate with either external or internal VCO. The high performance, combined with the ability to trade-off between power and performance, dual VCOs, dynamic digital delay, and holdover, allows for flexible high-performance clocking trees. The LMK04368-EP devices have gold bond wires, a temperature range of –55 to +105°C, and an SnPb lead finish.
Features
- Ambient temperature range of -55°C to 125°C
- 3255MHz maximum clock output frequency
- Multi-mode (dual PLL, single PLL, and clock distribution)
- 6GHz external VCO or distribution input
- Ultra-low noise at 2500MHz
- 54fs RMS jitter (12kHz to 20MHz)
- 64fs RMS jitter (100Hz to 20MHz)
- –157.6dBc/Hz noise floor
- Ultra-low noise at 3200MHz
- 61fs RMS jitter (12kHz to 20MHz)
- 67fs RMS jitter (100Hz to 100MHz)
- –156.5dBc/Hz noise floor
- PLL2
- PLL FOM of –230dBc/Hz
- PLL 1/f of –128dBc/Hz
- Phase detector rate up to 320MHz
- Two integrated VCOs of 2440MHz to 2600MHz and 2945MHz to 3255MHz
- Up to 14 differential device clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
- Up to 1 buffered VCXO/XO output
- LVPECL, LVDS, 2xLVCMOS programmable
- 1-1023 CLKOUT divider
- 1-8191 SYSREF divider
- 25ps step analog delay for SYSREF clocks
- Digital delay and dynamic digital delay for device clocks and SYSREF
- Holdover mode with PLL1
- 0-delay with PLL1 or PLL2
- High reliability
- Controlled baseline
- One assembly/test site
- One fabrication site
- Extended product life cycle
- Extended product-change notification
- Product traceability
Applications
- Military radar
- Electronic warfare
- Data converter clocking
- Wireless infrastructure
Additional Resources
Block Diagram
Related Development Tool
Texas Instruments LMK04368EPEVM Evaluation Module
Demonstrates the performance and features of the LMK04368-EP clock jitter cleaner.
Paskelbta: 2024-06-26
| Atnaujinta: 2024-09-04