Microsemi / Microchip Switchtec PFX PCIe Gen3 Fanout Switches
Microsemi / Microchip Switchtec PFX PCIe Gen3 Fanout Switches are compliant with PCIe Base Specification 3.1 and support up to 96 lanes, 24 virtual switch partitions, and 48 non-transparent bridges (NTBs). The series offers hot- and surprise-plug controllers for each port, advanced error containment, and comprehensive diagnostics and debug capabilities. Microsemi / Microchip Switchtec PFX PCIe Gen3 Fanout Switches provide simple hardware configuration and advanced diagnostics and debug capabilities. The switches enable PCIe solutions for a wide variety of systems, from flash-only Just a Bunch of Flash (JBOF) storage to general-purpose applications requiring low-power and high-reliability PCIe switching.
Features
- High-performance non-blocking switches
- Up to 174GB/s switching capacity
- 96-, 80-, 64-, 48-, 32-, and 24-lane variants
- Ports bifurcate from x2 to x16 lanes
- Up to 48 NTBs assignable to any port
- Logical non-transparent (NT) interconnect allows for larger topologies (up to 256 masters)
- Supports 1+1 and N+1 failover mechanisms
- NT address translation using direct windows and multiple sub-windows per BAR
- Supports multicast groups per port
- Error containment
- Advanced error reporting (AER) on all ports
- Downstream port containment (DPC) on all downstream ports
- Poisoned TLP blocking
- Completion timeout synthesis (CTS) to prevent error state in upstream host due to incomplete non-posted transactions
- Hot- and surprise-plug controllers per port
- GPIOs configurable for different cable/connector standards
- PCIe interfaces
- Passive, managed, and optical cables
- SFF-8644, SFF-8643, SFF-8639, OCuLink, and other connectors
- SHPC-enabled slot and edge connectors
- Diagnostics and debug
- Transaction layer packet (TLP) generator for testing and debugging of links and error handling
- Real-time eye capture
- Any-to-any port mirroring for debug purposes
- External loopback at PHY and TLP layers
- Errors, statistics, performance, and TLP latency counters
- Peripheral I/O interfaces
- Up to 11 two-wire interfaces (TWIs) with SMBus support
- Up to 2 SFF-8485-compliant SGPIO ports
- Up to 109 parallel GPIO pins
- Up to 4 UARTs
- JTAG and EJTAG interface
- High-speed I/O
- PCIe Gen3 8 GT/s
- Supports PCIe-compliant link training and manual PHY configuration
- Power management
- Active-state power management (ASPM)
- Software-controlled power management
- Package options
- FCBGA-650
- FCBGA-1311
Application Example
Related Products
Microchip Technology Switchtec™ PFX Gen 5 Fanout PCIe® Switches
Support up to 100 lanes, 52 ports, 26 virtual switch partitions, and 48 Non-Transparent Bridges.
Paskelbta: 2018-03-27
| Atnaujinta: 2024-07-03