Analog Devices Inc. AD4080 Differential SAR ADCs

Analog Devices AD4080 Differential SAR ADCs are high-speed, 20-bit, low-noise, low-distortion, easy drive, successive approximation register (SAR) analog-to-digital converters (ADCs). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio >90dBFS) at signal frequencies over 1MHz allows the AD4080 to operate for a wide variety of precision, wide-bandwidth data acquisition applications. Simplification of the input anti-alias filter configuration can be achieved by applying oversampling along with integrated digital filtering and decimation to decrease noise and lower the output data rate for applications that do not require the lowest latency of the AD4080.

The AD4080 Easy Drive reduces signal chain complexity and power consumption while facilitating greater channel density and flexibility in companion component selection. The ADCs' input structure was developed to minimize input-dependent signal currents, reducing converter-induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements compared to other high-speed data converters.

The ADI AD4080 incorporates several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regulators to develop ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can significantly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated into the package to guarantee optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint.

Features

High performance
- Throughput of 40MSPS, 46.25ns conversion latency
- INL of ±4ppm (typical), ±8ppm (maximum)
- SNR/THD
  - 93.6dB (typical)/-110dB (typical) at f_IN = 1kHz
  - 93.5dB (typical)/-104dB (typical) at f_IN = 1MHz
- Noise spectral density at -167.6dBFS/Hz
- 20-bit resolution, no missing codes
Low power at 79.3mW typical at 40MSPS with -0.5dBFS sine-wave input
Easy Drive, fully differential Input
- 6Vp-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current

Integrated, low-drift reference buffer and decoupling
Integrated V_CM generation
Digital features and data interface
- Conversion result from FIFO, 16K sample depth
- Digital averaging filter with up to 210 decimation
SPI configuration
Configurable data interface
- Single lane, DDR, serial LVDS, 800MBPS per lane
- Dual lane, DDR, serial LVDS, 400MBPS per lane
- Single/quad lane SPI data interface
Package
- 49-ball, 5mm x 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
Operating temperature range of -40°C to +85°C