Grįžti į GSI Technology

GSI Technology SigmaQuad-IVe ECCRAMs

GSI Technology SigmaQuad-IVe ECCRAMs are the Separate I/O half of the SigmaQuad-IVe/SigmaDDR-IVe family of high performance ECCRAMs. The devices are similar to GSI's third generation of networking SRAMs but offer several new features that help enable significantly higher performance. GSI's ECCRAMs implement an ECC algorithm that detects and corrects all single-bit memory errors, including those induced by SER events. These events include cosmic rays, alpha particles, etc. The resulting Soft Error Rate of these devices is anticipated to be <0.002 FITs/Mb. A 5-order-of-magnitude improvement over comparable SRAMs with no on-chip ECC, which typically have an SER of 200FITs/Mb or more.

Features

  • 4Mb x 36 and 8Mb x 18 organizations available
  • Organized as eight logical memory banks
  • 1333MHz maximum operating frequency
  • 1.333BT/s peak transaction rate (in billions per second)
  • 192Gb/s peak data bandwidth (in x36 devices)
  • Separate I/O DDR Data Buses
  • Non-multiplexed SDR Address Bus
  • One operation - Read or Write - per clock cycle
  • Certain address/bank restrictions on Read and Write ops
  • Burst of four Read and Write operations
  • 6-cycle Read Latency
  • On-chip ECC with virtually zero SER
  • Loopback signal timing training capability
  • 1.25V ~ 1.3V nominal core voltage
  • 1.2V ~ 1.3V POD I/O interface
  • Configuration registers
  • Configurable ODT (on-die termination)
  • ZQ pin for programmable driver impedance
  • ZT pin for programmable ODT impedance
  • IEEE 1149.1 JTAG-compliant Boundary Scan
  • 260-pin, 14x22mm, 1mm ball pitch, 6/6 RoHS-compliant BGA package

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Paskelbta: 2019-06-26 | Atnaujinta: 2023-04-21