ADN4651BRSZ

Analog Devices Isolation - All

ADN4650 / ADN4651 / ADN4652 LVDS Isolators

Analog Devices ADN4650/ADN4651/ADN4652 Dual Channel Low Voltage Differential Signaling (LVDS) Isolators operate up to 600Mbps with very low 70ps jitter. The ADN4650/ADN4651/ADN4652 isolators feature the iCoupler technology for high-speed operation. This technology provides galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers at full speed. The design allows for drop-in isolation of an LVDS signal chain. The LVDS and isolator circuits rely on a 2.5V supply for high-speed operation with low jitter. An integrated on-chip LDO provides the required 2.5V from an external 3.3V power supply. The devices are specified for a -40°C to +125°C industrial temperature range with 5kVrms isolation and 7.6mm creepage/clearance. To ensure safe, fast data transfer in harsh environments, the ADN4650/ADN4651/ADN4652 isolators meet 10kV peak surge protection requirements. The ADN4650/ADN4651/ADN4652 isolators are well-suited for analog front end (AFE) isolation, data-plane isolation, isolated high-speed clock and data links, and isolated SPI over LVDS.

ADN4651 LVDS Digital Isolators

Analog Devices ADN4651 low-voltage differential signal (LVDS) digital isolators are designed using the iCoupler® digital isolator technology for high-speed operation. With this technology, the ADN4651 isolators offer galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. The design of the ADN4651 series allows for drop-in isolation of an LVDS signal chain. The isolators operate with data rates up to 600Mbps, 70ps ultra-low jitter, and 4.5ns max. The isolators include a fail-safe mechanism to ensure a logic 1 on the corresponding LVDS driver output when the inputs are floating, short circuit, or terminate. The devices are specified for operation over a −40°C to +125°C industrial temperature range with 5kVrms isolation and 7.6mm creepage/clearance. The ADN4651 isolators are well-suited for analog front end (AFE) isolation, data-plane isolation, isolated high-speed clock and data links, and isolated SPI over LVDS.